The present invention relates generally to the field of semiconductor devices, and more particularly to a system for reducing power consumption in memory devices.
Memory systems are known in the art and used in nearly all microprocessor and digital equipment applications. Memory systems generally utilize different types of memory for different applications. Once such type of memory is Static Random Access Memory (xe2x80x9cSRAMxe2x80x9d). SRAM systems have the advantage of high speed and ease of use as compared to some other types of memory systems. In addition, SRAM systems using MOS technology exhibit extremely low standby power and do not require a refresh cycle to maintain the information stored in the SRAM system. These attributes make SRAM systems particularly desirable for portable equipment, such as laptop computers. As a result, SRAM arrays are becoming an increasingly large portion of many integrated circuits.
In an integrated circuit, SRAM systems are often organized into an array of memory cells, arranged in rows and columns. Generally, memory cells are set to one of two data states when storing a bit of information. Each memory cell may be referenced by a unique memory address, which includes a row address and a column address. The term xe2x80x9cwordlinexe2x80x9d generally refers to one or more conductors that correspond to a row of memory cells, whereas the term xe2x80x9cbitlinesxe2x80x9d generally refers to a set of conductors that correspond to a column of memory cells. A memory cell typically includes of pair of complementary ports, with each port connected to one of the two bitlines dedicated to that column. Memory devices commonly operate in a read mode and a write mode. When writing to a memory cell, the wordline is activated, thereby activating the entire row in the array of memory cells. A differential current is applied to the bitlines between the two complementary input/output ports of the memory cell. The memory cell is latched to a specific logic state with a logic high indicated on one port and a logic low indicated on the other port. When reading from a memory cell, the wordline is activated and the logic states on the bitlines associated with the memory cell is differentially sensed using a sense amplifier. The sense amplifier outputs an amplify signal corresponding to the logic state written to the memory cell.
The easiest way to lower the power consumption of a SRAM memory array is to lower the voltage. But, lowering the voltage reduces the performance and stability of the memory array. One method of reducing the power consumption of a memory device is to lower the supply voltage VDD for the memory array. The bitlines, which are connected to the memory cells, are pre-charged with the supply voltage and the supply voltage is then boosted to derive an array voltage, which is applied to the memory cells at a boosted level higher than the supply voltage. The memory cells are accessed by applying a wordline voltage that is greater than the supply voltage and less than the sum of the supply voltage and the threshold voltage of the access transistors. Although this method works, it is more difficult (more load) to drive VDD than it is to drive the wordline. Moreover, there are timing issues of VDD row relative to the wordline, which causes slower memory access.
As a result, there is a need for a system for reducing the power consumption of a memory device in an easier and more efficient manner.
The present invention provides a system for reducing the power consumption of a memory device in an easier and more efficient manner. More specifically, the present invention reduces the voltage to the memory array, thus reducing array IDDQ and reducing the power consumption of the memory device. To maintain performance and stability of the accessed cells, the voltage is raised to the accessed rows before accessing the memory cells. The access may also be pipelined in order to allow more time to raise the row supply voltage relative to the time for raising the word line voltage. For example, the row voltage is raised in a first cycle and the memory cell is accessed (raise wordline voltage) in the following cycle. With pipelining, there can be one access per cycle with one cycle latency. Additional latency/pipelining could be used if necessary. Note that the supply voltage could be raised to a block of rows containing the accessed row instead of only the addressed row. SRAM IDDQ can be lowered significantly by lowering row VDD, especially when row VDD is lowered relative to n-well. Resistance in row VDD does not significantly affect performance.
An SRAM array is provided, in which row VDD is lowered for the entire array except for the addressed row during active. VDD to the addressed row is restored to nominal for access. The read cycle needs to be long enough to include time to restore VDD row to the addressed row. If necessary, the read cycle can extend over multiple clock cycles. Note that multiple rows can be powered together. In addition, the voltage restoration and cell access can be pipelined (start restoration of VDD row to a second row while accessing a first row). Another option is simply to lower VDD to the array and wordline drivers, and allows more time for the sense amp latch. Raising the addressed VDD row becomes worthwhile if either: pipelining is used for faster cycles, or VDD row is lowered enough to make access very slow or impossible, e.g. to around VBOX low. Note that when VDD row is lowered significantly, the addressed VDD row may be raised to some value still below nominal for access.
More specifically, the present invention provides a method for reducing power consumption in a memory device containing a memory array having a number of memory cells by raising a supply voltage of a row of memory cells from a first voltage to a second voltage whenever the row of memory cells is selected for access and lowering the supply voltage of the row of selected memory cells from the second voltage to the first voltage after the row of selected memory cells has been accessed. The first voltage is low enough to reduce power consumption of the memory device, but is high enough to retain data stored in the memory device. The second voltage is a nominal operating voltage sufficient to access the row of selected memory cells while maintaining the performance and stability of the row of selected memory cells.
The present invention also provides an apparatus for reducing power consumption in a memory device containing a memory array having a number of memory cells. A first transistor and a second transistor are coupled in parallel between a supply voltage and a supply voltage for a row of memory cells. A row select line is coupled to the gate of the first transistor. The first transistor and the second transistor connected such that the supply voltage of the row of memory cells is raised from a first voltage to a second voltage whenever the row select line is enabled and lowering the supply voltage of the row of memory cells from the second voltage to the first voltage whenever the row select line is disabled.
In addition, a circuit can be added to pipeline the raising and lowering of the supply voltage of the row of memory cells. The pipeline circuit comprises includes a first latch and a second latch coupled to an address line, a first address decoder coupled to the first latch, a second address decoder coupled to the second latch, an OR (NOR) gate coupled to the output of the first address decoder and the second address decoder. The OR (NOR) gate provides a row select signal. Morevoer, a first pass circuit is coupled to the first address decoder, a second pass circuit is coupled to the second address decoder. The output of the first pass circuit and second pass circuit provide a wordline select signal.
The present invention also provides a system for reducing power consumption in a memory device containing a memory array having a number of memory cells and a power reduction circuit within each row of memory cells. Each power reduction circuit has a first transistor and a second transistor coupled in parallel between a supply voltage and a supply voltage for a row of memory cells, and a row select line coupled to the gate of the first transistor. The first transistor and the second transistor are connected such that the supply voltage of the row of memory cells is raised from a first voltage to a second voltage whenever the row select line is enabled and lowering the supply voltage of the row of memory cells from the second voltage to the first voltage whenever the row select line is disabled. A pipeline circuit may also be used in this system.
Other features and advantages of the present invention will be apparent to those of ordinary skill in the art upon reference to the following detailed description taken in conjunction with the accompanying drawings.